1. Field of the Invention
The present invention relates to a reliable semiconductor element and a fabrication method therefor. And more particularly, the invention relates to a reliable semiconductor element having high initial characteristics wherein short circuit or shunt occurring in the fabrication process is compensated, and a method and apparatus for fabricating the same.
2. Related Background Art
Photoelectric conversion elements in the form of semiconductors for converting light into electrical energy have been utilized extensively as voltage sources for electronic instruments such as electronic calculators or wristwatches, and have become accepted as practicable as alternative electric power sources for so-called fossil fuels such as petroleum or coal.
Photovoltaic elements are based on utilizing the diffusion potential arising in the pn junction region of semiconductors, wherein charge carriers consisting of electrons and positive holes are produced when the semiconductor such as silicon absorbs light, with the charge carriers drifting due to the internal electric field caused by the diffusion potential at the pn junction, and withdrawn externally. The fabrication of photovoltaic elements is carried out by processes used with the fabrication of semiconductor elements Specifically, single crystal silicon is fabricated in p-type or n-type by a crystal growth method such as a CZ method, with the single crystal being sliced into silicon wafers having a thickness of 300 .mu.m. The pn junction is then created by forming an opposite conductivity type layer by appropriate means such as that for diffusing a valence electron control agent to obtain an opposite conductivity type to that of the wafer.
When the fabrication method for photovoltaic elements uses the crystal-type semiconductor fabrication process as above described, the production costs are higher than those of the existing power generating methods.
For such reason, in order to put solar cells to practical use as a power source, lower cost is an important technical subject for which various studies have been made to obtain inexpensive materials or materials of high conversion efficiency. Such solar cell materials may include tetrahedral type semiconductors such as silicon, silicon-germanium, and silicon carbide, and Group II-VI compound semiconductors such as CdS and Cu.sub.2 or Group III-V compound semiconductors such as GaAs and GaAlAs. In particular, thin film solar cells using amorphous type semiconductors have been expected to be useful because of their advantages that semiconductors of large area can be fabricated than for single crystals, the film thickness of the semiconductor can be thin, and arbitrary substrate materials can be used for deposition.
An amorphous silicon type photovoltaic element (hereinafter referred to as a solar cell) typically has a structure wherein a substrate is provided with a lower electrode, on which at least one semiconductor junction of thin film type consisting of a p-type semiconductor region, an i-type semiconductor region, and an n-type semi-conductor region are laminated, and an upper electrode is provided thereon. Further, to increase the current collection efficiency, a grid electrode or a bus bar may be provided.
The amorphous silicon type photovoltaic element has lower conversion efficiency, because its film quality is degraded as compared with that of a crystal silicon photovoltaic element or a polycrystal silicon photovoltaic element, but to solve this problem, a so-called tandem cell or triple cell has been studied in which two or more semiconductor junctions are laminated in series.
When such solar cells are used, for example, to supply electric power to homes, an output of about 3 KW is generally required. When solar cells having conversion efficiency of 10% are used, the solar cell area must be as large as 30 m.sup.2 or greater. However, with the usual solar cell fabricating processes, it is difficult to fabricate nondefective solar cells over such a large area. For example, with polycrystalline semiconductors, low resistive regions may arise at grain boundary portions, or in thin film solar cells of amorphous silicon type, pin holes or defects may occur due to the presence of dust during forming of the semiconductor film, causing a shunt or short circuit, which is known to significantly decrease the conversion efficiency. The cause of a pin hole or a defect and its influence will be described in more detail. For example, in amorphous silicon type solar cells having thin film layers deposited on a stainless substrate, the substrate surface is not a completely smooth surface, and may comprise flaws, dents, or spike-like projections, or is provided with an irregularly surfaced back reflector for the purpose of irregularly reflecting light, so that a thin film semiconductor having a thickness of about 10 nm such as in the p-type or n-type semiconductor region cannot cover the surface entirely, or pin holes may arise due to contaminants produced during forming of the films. Also, the semiconductor material between a lower electrode and an upper electrode of a solar cell may be lost at a pin hole, placing the lower electrode and the upper electrode in direct contact, or a spike-like defect of the substrate may make contact with the upper electrode. When there is a shunt or short circuit of low resistance, even if the semiconductor material is not completely absent, the electric current generated by light will flow parallel to the upper electrode into a low resistive portion of the shunt or short circuit, causing generated current to be lost. With such current loss, the open circuit voltage of the solar cell decreases.
In amorphous silicon type solar cells, because of the typically high sheet resistance of the semiconductor itself, a transparent upper electrode is used over the entire surface of the semiconductor, or a conductive antireflection film made of SnO.sub.2 or ITO(In.sub.2 O.sub.3 +SnO.sub.2) is usually provided to suppress the surface reflection. Therefore, the electric current flowing into a defect is quite significant even if the defect is minute. Further, when the defect location is away from the grid electrode for current collection or the bus bar, the current loss is relatively small because of the great resistance when it flows into a defective portion, but conversely, when the defect is located under the grid electrode or bus bar, the electric current loss due to the defect is greater.
On the other hand, in the defective portion with the pin hole, electric charges generated by the photovoltaic element may not only leak into the defective portion, but also ionic substances are produced due to interaction with any water content, whereby by using the solar cell, the electric resistance at defective portions decreases gradually with time, and thus the conversion efficiency may be degraded.
When a short circuit occurs as above, the current loss can be reduced by removing or insulating the upper electrode at that region. A method of selectively removing the upper electrode in the shunt or short circuit portion has been disclosed in U.S. Pat. No. 4,729,970, which teaches a process wherein the solar cell is immersed in an electrolytic solution, and the short circuited portion is removed by etching while applying a bias to the solar cell. However, even if the upper electrode is removed by etching, a short circuit may occur again when the grid is provided in the shunt portion.
A solution for such problem is to raise the contact resistance with the transparent electrode, grid electrode, or bus bar by selectively covering only the defective portion with an insulator material or a material having high enough resistance to substantially prevent the shunt or short circuit, and this method serves as an effective means for preventing the decrease in conversion efficiency. A method of selectively covering with insulation only the defective portion includes detecting the defective portions of the solar cell with a detector, and thereafter applying an insulating material to the detected defective portions by using an applicator, as disclosed in U.S. Pat. No. 4,451,970. Or there is available a method as disclosed in U.S. Pat. No. 4,197,141 in which a polycrystal solar cell is immersed in an electrolytic solution to oxidize the crystal grain boundaries of the polycrystal or the defective portions caused by lattice mismatch by applying an electric field, depositing an insulating substance on the defective portions, or etching the defective portion.
The former invention, as disclosed, has a problem in that both the detector for defective portions and the applicator may constitute bulky apparatuses, which only allow detection in a greater range than the size of actual defects, and further the insulation may extend over unnecessary portions and be highly swollen, so that the grid contact cannot be printed thereon. Also, the latter invention, as disclosed, which is based on the concept of selectively depositing the insulating material, gives as an example anodizing of the defective portions of a gallium arsenide solar cell, but no disclosure of utility with silicon type solar cells is provided. Also, it includes depositing a metallic oxide such as aluminum, chromium, or copper, and no disclosure of the deposition of an organic polymer material is provided.
As above described, with the conventional method, the insulating material may deposit to a greater extent than necessary, so that the performance of the solar cell may be degraded. With either method, it is difficult to say that only the defective portions can be completely insulated with no other bad effects, whereby there is a problem that a remarkable reduction in performance cannot be avoided when it is applied to practical solar cells. Such a problem was also the case with TFT thin film semiconductors deposited in a large area.
An object of the present invention is to solve the aforementioned problems associated with semiconductor elements, and to provide a semiconductor element having excellent characteristics.
Another object of the present invention is to provide a fabrication method and apparatus for a semiconductor element which is more reliable and favorable for mass production.